This invention relates to power supply supervision circuits. More particularly, this invention relates to power supply supervision circuits that determine when the output of a power supply is insufficient to power a load by providing a logical LOW as an output.
A power supply supervision circuit traditionally monitors the amount of voltage that a power supply provides by comparing the supplied voltage to a pre-determined voltage threshold. If the supplied voltage is below this pre-determined voltage threshold then the power supervision circuit provides a logic LOW at an output (RESET node). In turn, the RESET node is connected to, and utilized by, the load (e.g., a system or circuit) that is being powered.
Traditional power supervision circuits require a supply voltage of at least 1 volt in order to hold the RESET node at a logic LOW. This requirement is due to a single NMOS transistor that is traditionally used to pull-down the RESET node to a logic LOW. When the supply voltage is less than the voltage threshold of the NMOS transistor, the RESET node no longer sinks current and, as a result, becomes a node with a large amount of impedance (a high-impedance node). As a result of this large impedance, erroneous leakage currents coupled to the RESET node may drive the voltage of the RESET node above the threshold that separates a logic LOW from a logic HIGH. Thus, a logic HIGH may be erroneously provided on the RESET node which, in turn, may falsely alert the load that the supply voltage is within regulation (providing a sufficient supply voltage) when the supply voltage is not within regulation (not providing a sufficient supply voltage).
Furthermore, if only a mid-scale voltage is created on a RESET node instead of, for example, a pure logic LOW (0 volts) then the load may operate in the middle of its voltage transfer characteristics. In doing so, more quiescent current may be consumed than desired. Each one of above conditions may lead to reliability problems in the load. For example, if the load is a microprocessor then the microprocessor may fail to operate properly.
As in another traditional approach, a low-valued pull-down resistor is connected between the RESET node and ground in an attempt to discharge the RESET node. A PMOS transistor is included in order to pull-up the RESET node when the power supply is sufficient to power the load. However, such a pull-up transistor occasionally does not allow a user to pull-up the RESET node to a particular voltage because the pull-up voltage is hard-wired into the circuit. Furthermore, there is a limit as to how small the external resistor may be before the resistor overcomes the pull-up strength of the PMOS transistor. Moreover, low power systems may suffer while the reset node is a logic HIGH because the resistor will continuously dissipate power. For example, if a 5 volt output is desired and a 100 K Ω pull-down resistor is used then the system must support an additional 50 μA load at the RESET node.
It is therefore desirable to provide improved power supervision circuits.